
AN428
28 Rev. 0.6
// - The maximum SCL clock rate will be ~1/3 the Timer1 overflow rate
// - Timer1 enabled
void Timer1_Init (void)
{
// Make sure the Timer can produce the appropriate frequency in 8-bit mode
// Supported SMBus Frequencies range from 10kHz to 100kHz. The CKCON register
// settings may need to change for frequencies outside this range.
TMOD = 0x20; // Timer1 in 8-bit auto-reload mode
TH1 = 0xFF - (SYSCLK/SMB_FREQUENCY/3) + 1; // 100kHz or 400kHz for SCL
TL1 = TH1; // Init Timer1
TR1 = 1; // Timer1 enabled
}
//-----------------------------------------------------------------------------
// Timer2_Init
//-----------------------------------------------------------------------------
//
// Return Value : None
// Parameters : None
//
// Timer2 configured for SCL low timeout detection as
// follows:
// - Timer2 in 16-bit auto-reload mode
// - SYSCLK/12 as Timer2 clock source
void Timer2_Init (void)
{
TMR2CN = 0x00; // Timer2 configured for 16-bit auto-
// reload, low-byte interrupt disabled
// Timer2 uses SYSCLK/12 (see CKCON)
TMR2RLL = 0x5F;
TMR2RLH = 0x88;
TMR2L = TMR2RLL;
TMR2H = TMR2RLH;
TF2LEN = 0;
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