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12 www.xilinx.com AC701 Evaluation Board

UG952 (v1.1) January 30, 2013

Chapter 1: AC701 Evaluation Board Features

DDR3 Memory Module

[Figure 1-2, callout 2]

The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module

(SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM)

for storing user code and data. The SODIMM socket has a perforated EMI shield

surrounding it as seen in

Figure 1-2.

• Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)

• Supply voltage: 1.5V

• Data path width: 64 bits

• Data rate: Up to 1,600 MT/s

The DDR3 interface is implemented across I/O banks 32, 33, and 34. Each bank is a 1.5V

high-performance (HP) bank. An external 0.75V reference VTTREF is provided for data

interface banks 32 and 34. Any interface connected to these banks that requires a reference

voltage must use this FPGA voltage reference. The connections between the DDR 3

memory and the FPGA are listed in

Table 1-4.

Table 1-4: DDR3 Memory Connections to the FPGA

U1 FPGA Pin Net Name

J1 DDR3 Memory

Pin Number Pin Name

M4 DDR3_A0 98 A0

J3 DDR3_A1 97 A1

J1 DDR3_A2 96 A2

L4 DDR3_A3 95 A3

K5 DDR3_A4 92 A4

M7 DDR3_A5 91 A5

K1 DDR3_A6 90 A6

M6 DDR3_A7 86 A7

H1 DDR3_A8 89 A8

K3 DDR3_A9 85 A9

N7 DDR3_A10 107 A10/AP

L5 DDR3_A11 84 A11

L7 DDR3_A12 83 A12_BC_N

N6 DDR3_A13 119 A13

L3 DDR3_A14 80 A14

K2 DDR3_A15 78 A15

N1 DDR3_BA0 109 BA0

M1 DDR3_BA1 108 BA1

H2 DDR3_BA2 79 BA2

AB6 DDR3_D0 5 DQ0

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 106 107

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