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AC701 Evaluation Board www.xilinx.com 51

UG952 (v1.1) January 30, 2013

Feature Descriptions

Table 1-24 lists the GPIO Connections to FPGA U1.

Table 1-24: GPIO Connections to FPGA U1

FPGA (U1) Pin Schematic Net Name GPIO Pin

User LEDs (Active High)

M26 GPIO_LED_0 DS2.2

T24 GPIO_LED_1 DS3.2

T25 GPIO_LED_2 DS4.2

R26 GPIO_LED_3 DS5.2

Directional Push-Button Switches (Active High)

P6 GPIO_SW_N SW3.3

U5 GPIO_SW_E SW4.3

T5 GPIO_SW_S SW5.3

R5 GPIO_SW_W SW7.3

U6 GPIO_SW_C SW6.3

CPU_RESET Push-Button Switches (Active High)

U4 CPU_RESET SW8.3

4-Pole DIP Switch (Active High)

R8 GPIO_DIP_SW0 SW2.1

P8 GPIO_DIP_SW1 SW2.2

R7 GPIO_DIP_SW2 SW2.3

R6 GPIO_DIP_SW3 SW2.4

Rotary Encoder Switch (Active High)

P20 ROTARY_INCB SW10.6

N21 ROTARY_PUSH SW10.5

N22 ROTARY_INCA SW10.1

User SMA Connectors

T8 USER_SMA_GPIO_P J33.1

T7 USER_SMA_GPIO_N J34.1

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 106 107

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Silicon Laboratories SI5324 Guía de usuario Pagina 51