
AC701 Evaluation Board www.xilinx.com 15
UG952 (v1.1) January 30, 2013
Feature Descriptions
AC4 DDR3_DM1 28 DM1
AA3 DDR3_DM2 46 DM2
U7 DDR3_DM3 63 DM3
G1 DDR3_DM4 136 DM4
F3 DDR3_DM5 153 DM5
G5 DDR3_DM6 170 DM6
H9 DDR3_DM7 187 DM7
W8 DDR3_DQS0_N 10 DQS0_N
V8 DDR3_DQS0_P 12 DQS0_P
AE5 DDR3_DQS1_N 27 DQS1_N
AD5 DDR3_DQS1_P 29 DQS1_P
AE1 DDR3_DQS2_N 45 DQS2_N
AD1 DDR3_DQS2_P 47 DQS2_P
V2 DDR3_DQS3_N 62 DQS3_N
V3 DDR3_DQS3_P 64 DQS3_P
B1 DDR3_DQS4_N 135 DQS4_N
C1 DDR3_DQS4_P 137 DQS4_P
A5 DDR3_DQS5_N 152 DQS5_N
B5 DDR3_DQS5_P 154 DQS5_P
H4 DDR3_DQS6_N 169 DQS6_N
J4 DDR3_DQS6_P 171 DQS6_P
G7 DDR3_DQS7_N 186 DQS7_N
H7 DDR3_DQS7_P 188 DQS7_P
R2 DDR3_ODT0 116 ODT0
U2 DDR3_ODT1 120 ODT1
N8 DDR3_RESET_B 30 RESET_B
T3 DDR3_S0_B 114 S0_B
T2 DDR3_S1_B 121 S1_B
U1
DDR3_TEMP_
EVENT
198 EVENT_B
R1 DDR3_WE_B 113 WE_B
T4 DDR3_CAS_B 115 CAS_B
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA Pin Net Name
J1 DDR3 Memory
Pin Number Pin Name
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