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AC701 Evaluation Board www.xilinx.com 31

UG952 (v1.1) January 30, 2013

Feature Descriptions

GTP Transceivers

[Figure 1-2, callout 11]

The AC701 board provides access to 8 GTP transceivers:

• Four of the GTP transceivers are wired to the PCI Express® x4 endpoint edge

connector (P1) fingers

• Two of the GTP transceivers are wired to the FMC HPC connector (J30)

• One GTP is wired to SMA connectors (RX: J46, J47 TX: J44, J45)

• One GTP is wired to the SFP/SFP+ Module connector (P3)

The GTP transceivers in 7 series FPGAs are grouped into four channels described as

Quads. The reference clock for a Quad can be sourced from the Quad above or Quad below

the GTP Quad of interest. There are two GTP Quads on the AC701 board with connectivity

as shown here:

• Quad 213

• Contains 4 GTP transceivers:

- GTP0 SFP

- GTP1 FMC HPC DP0

- GTP2 FMC HPC DP1

- GTP3 SMA TX/RX Connector Pairs

• MGTREFCLK0 Clock Mux U3 output

• MGTREFCLK1 Clock Mux U4 output

• Quad 216

• Contains 4 GTP transceivers for PCIe lanes 0-3

• MGTREFCLK0 PCIe edge connector clock

•MGTREFCLK1 NC

Table 1-12 lists the GTP interface connections to the FPGA (U1).

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 106 107

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Silicon Laboratories SI5324 Guía de usuario Pagina 31